An integrated semiconductor memory, for example a DRAM (Dynamic Random Access Memory) semiconductor memory, generally includes control connections for applying control signals, address connections for applying address signals, and data connections for applying data. In the event of a write access operation, a write command is applied to the control connections and an address signal is applied to the address connections. This makes it possible to activate at least one memory cell in a memory cell array of the integrated semiconductor memory for a write access operation.
The data to be stored is applied to the data connections which are connected to receiving circuits in the semiconductor memory. The characteristic variables of the specification for a receiving circuit for receiving data include the set-up times and hold times. The latter are used to specify the time for which a data item must be applied at least to one of the data connections in order to be able to read the data item into the semiconductor memory in a clear and reliable manner. As a result of the increase in the access speed and thus in the operating frequency during the development of semiconductor memories in recent years, the time window in which valid data is applied to the semiconductor memory has become increasingly small. The receiving circuits must therefore accept the data into the semiconductor memory from the data connections within a very small time window.
FIG. 1 shows an integrated circuit ES′ of a semiconductor memory, in which a differential amplifier D is connected to an input connection E1 for applying a reference signal VREF and to an input connection E2 for applying a data signal (e.g., an input signal) DQ. The differential amplifier D compares a level of the data signal DQ with a level of the reference signal VREF and generates, at the output, an output signal which has a high or low level, is amplified by downstream amplifiers V1 and V2 and is forwarded to an output connection A. From there, the amplified data signals are generally supplied, via read/write amplifiers, to a memory cell array of an integrated semiconductor memory.
As shown in FIG. 1, input signals for the integrated semiconductor memory, for example the data signals DQ, are received using a differential amplifier. The problem with this is, in particular, that the differential amplifier is not driven by differential input signals but rather by an input signal level and a constant reference signal level. In this case, different delays generally arise when receiving a rising or falling edge of the input signal. This consequently produces, at the output connection A, an output signal whose duty cycle is distorted with respect to the input signal. If, for example, the differential amplifier is supplied with an input signal which, during a clock period, has a high level for half of the period duration and a low level for the other half of the period duration, an output signal in which the high and low levels have different durations is produced at the output connection A.